From 44cff7a8975b2adbf2866718ec8c61ab0d9bd505 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Fri, 17 Aug 2018 15:38:59 +0800 Subject: cbtable: remove chromeos_acpi from cbtable Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/baytrail/include/soc/device_nvs.h | 3 --- src/soc/intel/baytrail/include/soc/nvs.h | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'src/soc/intel/baytrail/include') diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h index b4fe65e7d9..bc6f7ec5de 100644 --- a/src/soc/intel/baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/baytrail/include/soc/device_nvs.h @@ -19,9 +19,6 @@ #include #include -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define LPSS_NVS_SIO_DMA1 0 #define LPSS_NVS_I2C1 1 #define LPSS_NVS_I2C2 2 diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 21cdb142a4..715929d7ea 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -102,7 +102,7 @@ typedef struct global_nvs_t { /* Baytrail LPSS (0x1000) */ device_nvs_t dev; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ -- cgit v1.2.3