From bc69ae9823e9260bee6f2db557a6d26c683f4ad2 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 31 Oct 2013 10:46:56 -0500 Subject: baytrail: add lpss iosf functions and regs The low power subsystem devices have a lot of their configuration done in the IOSF sideband message space. Add support for these access methods. BUG=chrome-os-partner:23790 BRANCH=None TEST=Built and booted through depthcharge. Change-Id: I0dd52b952a16ef1280c29301164db041ee87f636 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/175440 Reviewed-by: Duncan Laurie Tested-by: Aaron Durbin Commit-Queue: Aaron Durbin Reviewed-on: http://review.coreboot.org/4921 Reviewed-by: Alexandru Gagniuc Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/iosf.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'src/soc/intel/baytrail/iosf.c') diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 7d420cc627..8016446338 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -165,3 +165,25 @@ void iosf_ushphy_write(int reg, uint32_t val) write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } + +uint32_t iosf_lpss_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_LPSS) | + IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_lpss_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_LPSS) | + IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +} -- cgit v1.2.3