From 26a682c9441b4f7312ff9f69d22029841aa245bd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Fri, 2 Aug 2019 06:13:22 +0300
Subject: intel/baytrail,broadwell: Move stage cache support function
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Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.

Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/baytrail/memmap.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'src/soc/intel/baytrail/memmap.c')

diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c
index 211f476712..94e91ca7a1 100644
--- a/src/soc/intel/baytrail/memmap.c
+++ b/src/soc/intel/baytrail/memmap.c
@@ -14,6 +14,7 @@
  */
 
 #include <cbmem.h>
+#include <stage_cache.h>
 #include <soc/iosf.h>
 #include <soc/smm.h>
 
@@ -26,3 +27,16 @@ void *cbmem_top(void)
 {
 	return (void *) smm_region_start();
 }
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+	char *smm_base;
+	/* 1MiB cache size */
+	const long cache_size = CONFIG_SMM_RESERVED_SIZE;
+
+	/* Ramstage cache lives in TSEG region which is the definition of
+	 * cbmem_top(). */
+	smm_base = cbmem_top();
+	*size = cache_size;
+	*base = &smm_base[smm_region_size() - cache_size];
+}
-- 
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