From ce727e18f0992126b7a27b8a51b426834e804390 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 12 Dec 2013 10:27:11 -0800 Subject: baytrail: allow ramstage_cache_location() usage in ramstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To prepare for caching reference code for S3 resume the ramstage cache needs to be accesible in ramstage as well. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/179776 Reviewed-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/5012 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/baytrail/stage_cache.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 src/soc/intel/baytrail/stage_cache.c (limited to 'src/soc/intel/baytrail/stage_cache.c') diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c new file mode 100644 index 0000000000..3bda56d968 --- /dev/null +++ b/src/soc/intel/baytrail/stage_cache.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +struct ramstage_cache *ramstage_cache_location(long *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = CONFIG_SMM_RESERVED_SIZE; + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + return (void *)&smm_base[smm_region_size() - cache_size]; +} -- cgit v1.2.3