From 157b189f6b97b6e9ecd8d29edbbd045fbbc231f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 16 Aug 2019 14:02:25 +0300 Subject: cpu/intel: Enter romstage without BIST MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/baytrail/include/soc/romstage.h | 1 - src/soc/intel/baytrail/romstage/romstage.c | 5 ++--- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/baytrail') diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index fffce7e317..3dc24f0777 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -25,7 +25,6 @@ #include struct romstage_params { - unsigned long bist; struct mrc_params *mrc_params; }; diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 6bf8aac9af..cf6a856b7b 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -115,10 +115,9 @@ static void spi_init(void) } /* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) +static void romstage_main(uint64_t tsc) { struct romstage_params rp = { - .bist = bist, .mrc_params = NULL, }; @@ -159,7 +158,7 @@ static void romstage_main(uint64_t tsc, uint32_t bist) */ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { - romstage_main(base_timestamp, bist); + romstage_main(base_timestamp); } static struct chipset_power_state power_state; -- cgit v1.2.3