From 4de1a31cb04f0363b6d257d9de392cdfe8d5644c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Fri, 15 Jan 2021 05:58:42 +0200
Subject: ACPI: Add acpi_reset_gnvs_for_wake()
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With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.

Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/soc/intel/baytrail/acpi.c     |  8 --------
 src/soc/intel/baytrail/ramstage.c | 23 ++++++++++++-----------
 2 files changed, 12 insertions(+), 19 deletions(-)

(limited to 'src/soc/intel/baytrail')

diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 682f9b4a43..445441e146 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
-#include <acpi/acpi_gnvs.h>
 #include <acpi/acpigen.h>
 #include <arch/ioapic.h>
 #include <device/mmio.h>
@@ -16,7 +15,6 @@
 #include <soc/iomap.h>
 #include <soc/irq.h>
 #include <soc/msr.h>
-#include <soc/nvs.h>
 #include <soc/pattrs.h>
 #include <soc/pm.h>
 
@@ -55,12 +53,6 @@ static acpi_cstate_t cstate_map[] = {
 	}
 };
 
-void soc_fill_gnvs(struct global_nvs *gnvs)
-{
-	/* Set unknown wake source */
-	gnvs->pm1i = -1;
-}
-
 int acpi_sci_irq(void)
 {
 	u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index f1401e2411..28aa588c01 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -121,37 +121,38 @@ static void fill_in_pattrs(void)
 static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps)
 {
 	uint16_t pm1;
+	int index;
+
 	pm1 = ps->pm1_sts & ps->pm1_en;
 
 	/* Scan for first set bit in PM1 */
-	for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
+	for (index = 0; index < 16; index++) {
 		if (pm1 & 1)
 			break;
 		pm1 >>= 1;
 	}
 
-	/* If unable to determine then return -1 */
-	if (gnvs->pm1i >= 16)
-		gnvs->pm1i = -1;
-
-	printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n",
-	       gnvs->pm1i);
+	if (index < 16)
+		gnvs->pm1i = index;
 }
 
 static void acpi_save_wake_source(void *unused)
 {
 	const struct chipset_power_state *ps;
-	struct global_nvs *gnvs = acpi_get_gnvs();
-	if (!gnvs)
-		return;
+	struct global_nvs *gnvs;
 
+	if (acpi_reset_gnvs_for_wake(&gnvs) < 0)
+		return;
 	if (acpi_pm_state_for_wake(&ps) < 0)
 		return;
 
 	pm_fill_gnvs(gnvs, ps);
+
+	printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n",
+	       gnvs->pm1i);
 }
 
-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, acpi_save_wake_source, NULL);
 
 static void baytrail_enable_2x_refresh_rate(void)
 {
-- 
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