From 76cedd2c292352d7dbd45fab70ec272e476d0910 Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@google.com>
Date: Sat, 2 May 2020 10:24:23 -0700
Subject: acpi: Move ACPI table support out of arch/x86 (3/5)

This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.

In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'

BUG=b:155428745

Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
---
 src/soc/intel/baytrail/acpi.c             | 4 ++--
 src/soc/intel/baytrail/ehci.c             | 2 +-
 src/soc/intel/baytrail/elog.c             | 2 +-
 src/soc/intel/baytrail/include/soc/acpi.h | 2 +-
 src/soc/intel/baytrail/include/soc/pmc.h  | 2 +-
 src/soc/intel/baytrail/northcluster.c     | 2 +-
 src/soc/intel/baytrail/pmutil.c           | 2 +-
 src/soc/intel/baytrail/ramstage.c         | 2 +-
 src/soc/intel/baytrail/refcode.c          | 2 +-
 src/soc/intel/baytrail/romstage/raminit.c | 2 +-
 src/soc/intel/baytrail/southcluster.c     | 4 ++--
 src/soc/intel/baytrail/xhci.c             | 2 +-
 12 files changed, 14 insertions(+), 14 deletions(-)

(limited to 'src/soc/intel/baytrail')

diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 426c2de95a..eb94d39f59 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <device/mmio.h>
 #include <arch/smp/mpspec.h>
 #include <cbmem.h>
diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
index dc9855ddf8..06534d06ab 100644
--- a/src/soc/intel/baytrail/ehci.c
+++ b/src/soc/intel/baytrail/ehci.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c
index 1401649552..6ce90a4b5a 100644
--- a/src/soc/intel/baytrail/elog.c
+++ b/src/soc/intel/baytrail/elog.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <stdint.h>
 #include <console/console.h>
 #include <cbmem.h>
diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h
index 3da67ebf76..842049a283 100644
--- a/src/soc/intel/baytrail/include/soc/acpi.h
+++ b/src/soc/intel/baytrail/include/soc/acpi.h
@@ -4,7 +4,7 @@
 #ifndef _BAYTRAIL_ACPI_H_
 #define _BAYTRAIL_ACPI_H_
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <soc/nvs.h>
 
 void acpi_fill_in_fadt(acpi_fadt_t *fadt);
diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h
index 0161f67038..274e7a75b6 100644
--- a/src/soc/intel/baytrail/include/soc/pmc.h
+++ b/src/soc/intel/baytrail/include/soc/pmc.h
@@ -4,7 +4,7 @@
 #ifndef _BAYTRAIL_PMC_H_
 #define _BAYTRAIL_PMC_H_
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 
 #define IOCOM1		0x3f8
 
diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c
index d83be9f826..64d528f1cb 100644
--- a/src/soc/intel/baytrail/northcluster.c
+++ b/src/soc/intel/baytrail/northcluster.c
@@ -6,7 +6,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <stddef.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index aa56a2ebb2..e815a9730d 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -2,7 +2,7 @@
 /* This file is part of the coreboot project. */
 
 #include <stdint.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <arch/io.h>
 #include <bootmode.h>
 #include <device/device.h>
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 9036e103fc..7147f18449 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -2,7 +2,7 @@
 /* This file is part of the coreboot project. */
 
 #include <arch/cpu.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/intel/microcode.h>
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
index 5f6dce875f..39803dea4e 100644
--- a/src/soc/intel/baytrail/refcode.c
+++ b/src/soc/intel/baytrail/refcode.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <console/streams.h>
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 3ebf8fff2a..68b8c0e0bb 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -2,7 +2,7 @@
 /* This file is part of the coreboot project. */
 
 #include <stddef.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <assert.h>
 #include <cbfs.h>
 #include <cbmem.h>
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 3f83e08a4c..7f651b30ee 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -5,7 +5,7 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -26,7 +26,7 @@
 #include <soc/ramstage.h>
 #include <soc/spi.h>
 #include "chip.h"
-#include <arch/acpigen.h>
+#include <acpi/acpigen.h>
 
 static inline void
 add_mmio_resource(struct device *dev, int i, unsigned long addr,
diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c
index 473be2fcc3..347c796414 100644
--- a/src/soc/intel/baytrail/xhci.c
+++ b/src/soc/intel/baytrail/xhci.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-- 
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