From 8e23bac97ec66a49f9ddb1a4069e4e68666833fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 17 Aug 2019 06:47:50 +0300 Subject: intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove cases of __PRE_RAM__ and other preprocessor guards. Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928 Reviewed-by: Furquan Shaikh Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/include/soc/msr.h | 1 + src/soc/intel/baytrail/include/soc/ramstage.h | 1 - src/soc/intel/baytrail/include/soc/romstage.h | 6 ------ src/soc/intel/baytrail/romstage/romstage.c | 4 +++- src/soc/intel/baytrail/tsc_freq.c | 9 --------- 5 files changed, 4 insertions(+), 17 deletions(-) (limited to 'src/soc/intel/baytrail') diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index e39758c64b..5038bf87db 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -40,5 +40,6 @@ /* Read BCLK from MSR */ unsigned bus_freq_khz(void); +void set_max_freq(void); #endif /* _BAYTRAIL_MSR_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index d20859d055..f98a79b2ea 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -23,7 +23,6 @@ * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); void baytrail_init_cpus(struct device *dev); -void set_max_freq(void); void southcluster_enable_dev(struct device *dev); #if CONFIG(HAVE_REFCODE_BLOB) void baytrail_run_reference_code(void); diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 3dc24f0777..8ea2d699c7 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -35,12 +35,6 @@ void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); void punit_init(void); -void set_max_freq(void); - -#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif #endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index cf6a856b7b..7a413d9c1d 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -131,7 +132,8 @@ static void romstage_main(uint64_t tsc) tco_disable(); - byt_config_com1_and_enable(); + if (CONFIG(ENABLE_BUILTIN_COM1)) + byt_config_com1_and_enable(); console_init(); diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index f9c3014273..5b2d13599d 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -47,13 +47,6 @@ unsigned long tsc_freq_mhz(void) return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; } -#if !defined(__SMM__) -#if !defined(__PRE_RAM__) -#include -#else -#include -#endif - void set_max_freq(void) { msr_t perf_ctl; @@ -76,5 +69,3 @@ void set_max_freq(void) wrmsr(IA32_PERF_CTL, perf_ctl); } - -#endif /* __SMM__ */ -- cgit v1.2.3