From faf20d30a6e451d45e29613e3f4603dc72771843 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 14 Aug 2019 05:41:41 +0300 Subject: soc/intel: Rename some SMM support functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/cpu.c | 7 ++++--- src/soc/intel/baytrail/gpio.c | 2 +- src/soc/intel/baytrail/include/soc/smm.h | 11 ++++------- src/soc/intel/baytrail/pcie.c | 2 +- src/soc/intel/baytrail/smm.c | 11 ++++++----- 5 files changed, 16 insertions(+), 17 deletions(-) (limited to 'src/soc/intel/baytrail') diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index ebc4c22667..4cb0a066e5 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -17,7 +17,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -25,7 +27,6 @@ #include #include #include -#include #include #include @@ -198,10 +199,10 @@ static const struct mp_ops mp_ops = { .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = southcluster_smm_clear_state, + .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = relocation_handler, - .post_mp_init = southcluster_smm_enable_smi, + .post_mp_init = smm_southbridge_enable_smi, }; void baytrail_init_cpus(struct device *dev) diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 8d9ce0075e..3460a5f049 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -190,7 +190,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, route_reg |= ROUTE_SCI << (2 * (i + 8)); } } - southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); + smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); } static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], diff --git a/src/soc/intel/baytrail/include/soc/smm.h b/src/soc/intel/baytrail/include/soc/smm.h index ac0910f306..29b7946467 100644 --- a/src/soc/intel/baytrail/include/soc/smm.h +++ b/src/soc/intel/baytrail/include/soc/smm.h @@ -16,6 +16,8 @@ #ifndef _BAYTRAIL_SMM_H_ #define _BAYTRAIL_SMM_H_ +#include + /* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig * is included after chipset code. This causes the chipset's Kconfig to be * clobbered by the arch/x86/Kconfig if they have the same name. */ @@ -29,17 +31,12 @@ static inline int smm_region_size(void) uintptr_t smm_region_start(void); -#if !defined(__PRE_RAM__) && !defined(__SMM___) -#include -void southcluster_smm_clear_state(void); -void southcluster_smm_enable_smi(void); -void southcluster_smm_save_param(int param, uint32_t data); -#endif - enum { SMM_SAVE_PARAM_GPIO_ROUTE = 0, SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, SMM_SAVE_PARAM_COUNT }; +void smm_southcluster_save_param(int param, uint32_t data); + #endif /* _BAYTRAIL_SMM_H_ */ diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index b2b2d3c3b4..6dc0346b23 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -215,7 +215,7 @@ static void byt_pcie_enable(struct device *dev) strpfusecfg = pci_read_config32(dev, STRPFUSECFG); if (config->pcie_wake_enable) - southcluster_smm_save_param( + smm_southcluster_save_param( SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); } diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 42bc518f36..4f019229e4 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -27,12 +28,12 @@ /* Save settings which will be committed in SMI functions. */ static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; -void southcluster_smm_save_param(int param, uint32_t data) +void smm_southcluster_save_param(int param, uint32_t data) { smm_save_params[param] = data; } -void southcluster_smm_clear_state(void) +void smm_southbridge_clear_state(void) { uint32_t smi_en; @@ -57,7 +58,7 @@ void southcluster_smm_clear_state(void) clear_pmc_status(); } -static void southcluster_smm_route_gpios(void) +static void smm_southcluster_route_gpios(void) { u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; @@ -82,7 +83,7 @@ static void southcluster_smm_route_gpios(void) outl(alt_gpio_reg, alt_gpio_smi); } -void southcluster_smm_enable_smi(void) +void smm_southbridge_enable_smi(void) { uint16_t pm1_events = PWRBTN_EN | GBL_EN; @@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void) disable_gpe(PME_B0_EN); /* Set up the GPIO route. */ - southcluster_smm_route_gpios(); + smm_southcluster_route_gpios(); /* Enable SMI generation: * - on APMC writes (io 0xb2) -- cgit v1.2.3