From 2c63017ca356bd245b3b09d1001586c019f5fa05 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Tue, 2 Apr 2019 15:06:29 +0200 Subject: soc/intel/braswell: Correct serial IRQ support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Serial IRQ was configured in quiet mode, but not enabled. Enable serial IRQ and use 'enum seriirq_mode' as a devicetree option. Function sc_enable_serial_irqs() is added to enabled serial IRQs. enable_serirq_quiet_mode() is renamed to sc_set_serial_irqs_mode(). This function use the 'serirq_mode' to set the mode. The call to this function is moved from finalize to init having serial IRQs enable in early stage. Serial IRQs must be enabled in continuous mode for at least one frame before switching into quiet mode. BUG=N/A TEST=Portwell PQ7-M107 Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/29398 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/soc/intel/braswell/chip.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/braswell/chip.h') diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 9fde4d12a6..4afaf44417 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,6 +25,7 @@ #include #include +#include #include #define SVID_CONFIG1 1 @@ -54,6 +56,8 @@ struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; + enum serirq_mode serirq_mode; + /* Disable SLP_X stretching after SUS power well loss. */ int disable_slp_x_stretch_sus_fail; -- cgit v1.2.3