From 32471729d9ebbabe809711ec55568925c6ce2070 Mon Sep 17 00:00:00 2001
From: Lee Leahy <leroy.p.leahy@intel.com>
Date: Mon, 20 Apr 2015 15:20:28 -0700
Subject: Braswell: Add Braswell SOC support

Add the files to support the Braswell SOC.

BRANCH=none
BUG=None
TEST=Build for a Braswell platform

Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/braswell/elog.c | 49 +++++++++++++++++--------------------------
 1 file changed, 19 insertions(+), 30 deletions(-)

(limited to 'src/soc/intel/braswell/elog.c')

diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c
index 4fa92f7a9a..1626d0f8b3 100644
--- a/src/soc/intel/braswell/elog.c
+++ b/src/soc/intel/braswell/elog.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -20,15 +21,15 @@
 
 #include <arch/io.h>
 #include <arch/acpi.h>
-#include <stdint.h>
-#include <console/console.h>
 #include <cbmem.h>
+#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <elog.h>
 #include <soc/iomap.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
+#include <stdint.h>
 
 static void log_power_and_resets(const struct chipset_power_state *ps)
 {
@@ -37,29 +38,23 @@ static void log_power_and_resets(const struct chipset_power_state *ps)
 		elog_add_event(ELOG_TYPE_PWROK_FAIL);
 	}
 
-	if (ps->gen_pmcon1 & SUS_PWR_FLR) {
+	if (ps->gen_pmcon1 & SUS_PWR_FLR)
 		elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
-	}
 
-	if (ps->gen_pmcon1 & RPS) {
+	if (ps->gen_pmcon1 & RPS)
 		elog_add_event(ELOG_TYPE_RTC_RESET);
-	}
 
-	if (ps->tco_sts & SECOND_TO_STS) {
+	if (ps->tco_sts & SECOND_TO_STS)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
-	}
 
-	if (ps->pm1_sts & PRBTNOR_STS) {
+	if (ps->pm1_sts & PRBTNOR_STS)
 		elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
-	}
 
-	if (ps->gen_pmcon1 & SRS) {
+	if (ps->gen_pmcon1 & SRS)
 		elog_add_event(ELOG_TYPE_RESET_BUTTON);
-	}
 
-	if (ps->gen_pmcon1 & GEN_RST_STS) {
+	if (ps->gen_pmcon1 & GEN_RST_STS)
 		elog_add_event(ELOG_TYPE_SYSTEM_RESET);
-	}
 }
 
 static void log_wake_events(const struct chipset_power_state *ps)
@@ -74,33 +69,27 @@ static void log_wake_events(const struct chipset_power_state *ps)
 	/* Mask off disabled events. */
 	gpe0_sts = ps->gpe0_sts & ps->gpe0_en;
 
-	if (ps->pm1_sts & WAK_STS) {
+	if (ps->pm1_sts & WAK_STS)
 		elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
-		                    acpi_is_wakeup_s3() ? 3 : 5);
-	}
+				    acpi_slp_type == 3 ? 3 : 5);
 
-	if (ps->pm1_sts & PWRBTN_STS) {
+	if (ps->pm1_sts & PWRBTN_STS)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
-	}
 
-	if (ps->pm1_sts & RTC_STS) {
+	if (ps->pm1_sts & RTC_STS)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
-	}
 
-	if (gpe0_sts & PME_B0_EN) {
+	if (gpe0_sts & PME_B0_EN)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
-	}
 
-	if (gpe0_sts & pcie_wake_mask) {
+	if (gpe0_sts & pcie_wake_mask)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
-	}
 
 	gpio_mask = SUS_GPIO_STS0;
 	i = 0;
 	while (gpio_mask) {
-		if (gpio_mask & gpe0_sts) {
+		if (gpio_mask & gpe0_sts)
 			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
-		}
 		gpio_mask <<= 1;
 		i++;
 	}
@@ -111,8 +100,8 @@ void southcluster_log_state(void)
 	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
 
 	if (ps == NULL) {
-		printk(BIOS_DEBUG, "Not logging power state information. "
-			"Power state not found in cbmem.\n");
+		printk(BIOS_DEBUG,
+			"Not logging power state information. Power state not found in cbmem.\n");
 		return;
 	}
 
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