From 32471729d9ebbabe809711ec55568925c6ce2070 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Mon, 20 Apr 2015 15:20:28 -0700 Subject: Braswell: Add Braswell SOC support Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/10051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/braswell/romstage/Makefile.inc | 9 +- src/soc/intel/braswell/romstage/cache_as_ram.inc | 284 -------------------- src/soc/intel/braswell/romstage/early_spi.c | 19 +- src/soc/intel/braswell/romstage/gfx.c | 50 ---- src/soc/intel/braswell/romstage/pmc.c | 51 +--- src/soc/intel/braswell/romstage/raminit.c | 185 ------------- src/soc/intel/braswell/romstage/romstage.c | 318 +++++++---------------- src/soc/intel/braswell/romstage/uart.c | 38 --- 8 files changed, 114 insertions(+), 840 deletions(-) delete mode 100644 src/soc/intel/braswell/romstage/cache_as_ram.inc delete mode 100644 src/soc/intel/braswell/romstage/gfx.c delete mode 100644 src/soc/intel/braswell/romstage/raminit.c delete mode 100644 src/soc/intel/braswell/romstage/uart.c (limited to 'src/soc/intel/braswell/romstage') diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index 345037d51f..4149d2263a 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,7 +1,4 @@ -cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc -romstage-y += romstage.c -romstage-y += raminit.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c -romstage-y += gfx.c +romstage-y += early_spi.c romstage-y += pmc.c -romstage-y += early_spi.c \ No newline at end of file +romstage-y += romstage.c + diff --git a/src/soc/intel/braswell/romstage/cache_as_ram.inc b/src/soc/intel/braswell/romstage/cache_as_ram.inc deleted file mode 100644 index 7c6a67faff..0000000000 --- a/src/soc/intel/braswell/romstage/cache_as_ram.inc +++ /dev/null @@ -1,284 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include -#include -#include -#include - -/* The full cache-as-ram size includes the cache-as-ram portion from coreboot - * and the space used by the reference code. These 2 values combined should - * be a power of 2 because the MTRR setup assumes that. */ -#define CACHE_AS_RAM_SIZE \ - (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - -/* Cache all of CBFS just below 4GiB as Write-Protect type. */ -#define CODE_CACHE_SIZE (CONFIG_CBFS_SIZE) -#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) -#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) -#define CPU_PHYSMASK_HI ((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) - -#define NoEvictMod_MSR 0x2e0 -#define BBL_CR_CTL3_MSR 0x11e -#define MCG_CAP_MSR 0x179 - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* All CPUs need to be in Wait for SIPI state */ -wait_for_sipi: - movl (%esi), %eax - bt $12, %eax - jc wait_for_sipi - - post_code(0x21) - /* Configure the default memory type to uncacheable as well as disable - * fixed and variable range mtrrs. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - post_code(0x22) - /* Zero the variable MTRRs. */ - movl $MCG_CAP_MSR, %ecx - rdmsr - movzx %al, %ebx - /* First variable MTRR. */ - movl $0x200, %ecx - xorl %eax, %eax - xorl %edx, %edx - 1: - wrmsr - inc %ecx - dec %ebx - jnz 1b - - /* Zero out all fixed range and variable range MTRRs. */ - movl $fixed_mtrr_table, %esi - movl $((fixed_mtrr_table_end - fixed_mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx - 1: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz 1b - - post_code(0x23) - /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - post_code(0x24) - /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x25) - /* Set code caching up for romstage. */ - movl $(MTRRphysBase_MSR(1)), %ecx - movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - - movl $(MTRRphysMask_MSR(1)), %ecx - movl $(CODE_CACHE_MASK | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x26) - - /* Enable the L2 cache. */ - movl $BBL_CR_CTL3_MSR, %ecx - rdmsr - orl $0x100, %eax - wrmsr - - post_code(0x27) - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $1, %eax - wrmsr - - post_code(0x28) - - /* Clear the cache memory region. This will also fill up the cache */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - xorl %eax, %eax - rep stosl - - /* enable no evict mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $2, %eax - wrmsr - - post_code(0x29) - - /* Setup the stack. */ - movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax - movl %eax, %esp - - /* Push the initial TSC value from boot block. The low 32 bits are - * in mm0, and the high 32 bits are in mm1. */ - movd %mm1, %eax - pushl %eax - movd %mm0, %eax - pushl %eax - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - -before_romstage: - post_code(0x2a) - /* Call romstage.c main function. */ - call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. It also contains the information - * for setting up MTRRs. */ - movl %eax, %ebx - - post_code(0x2b) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x2c) - - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~MTRRdefTypeEn), %eax - wrmsr - - invd - - post_code(0x2d) - - /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - andl $~2, %eax - wrmsr - - /* Disable the no eviction mode */ - rdmsr - andl $~1, %eax - wrmsr - - post_code(0x2e) - - /* Setup stack as indicated by return value from ramstage_main(). */ - movl %ebx, %esp - - /* Get number of MTRRs. */ - popl %ebx - movl $MTRRphysBase_MSR(0), %ecx -1: - testl %ebx, %ebx - jz 1f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 1b -1: - post_code(0x2f) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x30) - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x31) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call romstage_after_car - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -/* Fixed MTRRs */ -fixed_mtrr_table: - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F -fixed_mtrr_table_end: diff --git a/src/soc/intel/braswell/romstage/early_spi.c b/src/soc/intel/braswell/romstage/early_spi.c index 773a4a2f67..31be1e9942 100644 --- a/src/soc/intel/braswell/romstage/early_spi.c +++ b/src/soc/intel/braswell/romstage/early_spi.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. All rights reserved. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -26,16 +27,18 @@ #include #include -#define SPI_CYCLE_DELAY 10 /* 10us */ -#define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */ +#define SPI_CYCLE_DELAY 10 /* 10us */ +#define SPI_CYCLE_TIMEOUT (400000 / SPI_CYCLE_DELAY) /* 400ms */ -#define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x)) -#define SPI16(x) *((volatile u16 *)(SPI_BASE_ADDRESS + x)) -#define SPI32(x) *((volatile u32 *)(SPI_BASE_ADDRESS + x)) +#define SPI8(x) (*((volatile u8 *)(SPI_BASE_ADDRESS + (x)))) +#define SPI16(x) (*((volatile u16 *)(SPI_BASE_ADDRESS + (x)))) +#define SPI32(x) (*((volatile u32 *)(SPI_BASE_ADDRESS + (x)))) -/* Minimal set of commands to read wpsr from SPI. Don't use this code outside +/* + * Minimal set of commands to read wpsr from SPI. Don't use this code outside * romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. */ + * Returns 0 on success, < 0 on failure. + */ int early_spi_read_wpsr(u8 *sr) { int timeout = SPI_CYCLE_TIMEOUT; @@ -49,7 +52,7 @@ int early_spi_read_wpsr(u8 *sr) SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; /* Wait for error / complete status */ - while(timeout--) { + while (timeout--) { u16 status = SPI16(SSFS); if (status & FLASH_CYCLE_ERROR) { printk(BIOS_ERR, "SPI rdsr failed\n"); diff --git a/src/soc/intel/braswell/romstage/gfx.c b/src/soc/intel/braswell/romstage/gfx.c deleted file mode 100644 index 434bc9cad8..0000000000 --- a/src/soc/intel/braswell/romstage/gfx.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include -#include -#include -#include - -void gfx_init(void) -{ - uint32_t ggc; - uint8_t msac; - const unsigned int gfx_dev = PCI_DEV(0, GFX_DEV, GFX_FUNC); - - /* The GFX device needs to set the aperture, gtt stolen size, and - * graphics stolen memory stolen size before running MRC. For now - * just hard code the defaults. Options can be added to the device - * tree if needed. */ - - ggc = pci_read_config32(gfx_dev, GGC); - msac = pci_read_config8(gfx_dev, MSAC); - - ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK); - /* 32MB GSM is not supported with #include -#include -#include -#include #include -#include -#include -#include -#include #include -#include "../chip.h" void tco_disable(void) { @@ -38,44 +30,3 @@ void tco_disable(void) reg |= TCO_TMR_HALT; outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); } - -/* This sequence signals the PUNIT to start running. */ -void punit_init(void) -{ - uint32_t reg; - uint8_t rid; - const struct device *dev; - const struct soc_intel_baytrail_config *cfg = NULL; - - rid = pci_read_config8(IOSF_PCI_DEV, REVID); - dev = dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)); - - if (dev) - cfg = dev->chip_info; - - reg = iosf_punit_read(SB_BIOS_CONFIG); - /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ - reg |= SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; - /* Configure VR low power mode for C0 and above. */ - if (rid >= RID_C_STEPPING_START && cfg != NULL && - (cfg->vnn_ps2_enable || cfg->vcc_ps2_enable)) { - printk(BIOS_DEBUG, "Enabling VR PS2 mode: "); - if (cfg->vnn_ps2_enable) { - reg |= SB_BIOS_CONFIG_PS2_EN_VNN; - printk(BIOS_DEBUG, "VNN "); - } - if (cfg->vcc_ps2_enable) { - reg |= SB_BIOS_CONFIG_PS2_EN_VCC; - printk(BIOS_DEBUG, "VCC "); - } - printk(BIOS_DEBUG, "\n"); - } - iosf_punit_write(SB_BIOS_CONFIG, reg); - - /* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */ - reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE; - pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); - reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | - IOSF_REG(BIOS_RESET_CPL) | IOSF_BYTE_EN_0; - pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); -} diff --git a/src/soc/intel/braswell/romstage/raminit.c b/src/soc/intel/braswell/romstage/raminit.c deleted file mode 100644 index d4f1711e36..0000000000 --- a/src/soc/intel/braswell/romstage/raminit.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void reset_system(void) -{ - warm_reset(); - halt(); -} - -static void enable_smbus(void) -{ - uint32_t reg; - const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); - - /* SMBus I/O BAR */ - reg = SMBUS_BASE_ADDRESS | 2; - pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); - /* Enable decode of I/O space. */ - reg = pci_read_config16(smbus_dev, PCI_COMMAND); - reg |= 0x1; - pci_write_config16(smbus_dev, PCI_COMMAND, reg); - /* Enable Host Controller */ - reg = pci_read_config8(smbus_dev, 0x40); - reg |= 1; - pci_write_config8(smbus_dev, 0x40, reg); - - /* Configure pads to be used for SMBus */ - score_select_func(PCU_SMB_CLK_PAD, 1); - score_select_func(PCU_SMB_DATA_PAD, 1); -} - -static void ABI_X86 send_to_console(unsigned char b) -{ - do_putchar(b); -} - -static void print_dram_info(void) -{ - const int mrc_ver_reg = 0xf0; - const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); - uint32_t reg; - int num_channels; - int speed; - uint32_t ch0; - uint32_t ch1; - - reg = pci_read_config32(soc_dev, mrc_ver_reg); - - printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); - - /* Number of channels enabled and DDR3 type. Determine number of - * channels by keying of the rank enable bits [3:0]. * */ - ch0 = iosf_dunit_ch0_read(DRP); - ch1 = iosf_dunit_ch1_read(DRP); - num_channels = 0; - if (ch0 & DRP_RANK_MASK) - num_channels++; - if (ch1 & DRP_RANK_MASK) - num_channels++; - - printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, - (reg & (1 << 22)) ? "LP" : ""); - - /* DRAM frequency -- all channels run at same frequency. */ - reg = iosf_dunit_read(DTR0); - switch (reg & 0x3) { - case 0: - speed = 800; break; - case 1: - speed = 1066; break; - case 2: - speed = 1333; break; - case 3: - speed = 1600; break; - } - printk(BIOS_INFO, "%dMHz\n", speed); -} - -void raminit(struct mrc_params *mp, int prev_sleep_state) -{ - int ret; - mrc_wrapper_entry_t mrc_entry; - const struct mrc_saved_data *cache; - - /* Fill in default entries. */ - mp->version = MRC_PARAMS_VER; - mp->console_out = &send_to_console; - mp->prev_sleep_state = prev_sleep_state; - mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); - - /* Default to 2GiB IO hole. */ - if (!mp->io_hole_mb) - mp->io_hole_mb = 2048; - - if (recovery_mode_enabled()) { - printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (!mrc_cache_get_current(&cache)) { - mp->saved_data_size = cache->size; - mp->saved_data = &cache->data[0]; - } else if (prev_sleep_state == 3) { - /* If waking from S3 and no cache then. */ - printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); - reset_system(); - } else { - printk(BIOS_DEBUG, "No MRC cache found.\n"); -#if CONFIG_EC_GOOGLE_CHROMEEC - if (prev_sleep_state == 0) { - /* Ensure EC is running RO firmware. */ - google_chromeec_check_ec_image(EC_IMAGE_RO); - } -#endif - } - - /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL) == NULL) { - printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); - return; - } - - /* - * The entry point is currently the first instruction. Handle the - * case of an ELF file being put in the cbfs by setting the entry - * to the CONFIG_MRC_BIN_ADDRESS. - */ - mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS; - - if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) - enable_smbus(); - - ret = mrc_entry(mp); - - print_dram_info(); - - if (prev_sleep_state != 3) { - cbmem_initialize_empty(); - } else if (cbmem_initialize()) { - #if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); - /* Failed S3 resume, reset to come up cleanly */ - reset_system(); - #endif - } - - printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, - mp->data_to_save_size); - - if (mp->data_to_save != NULL && mp->data_to_save_size > 0) - mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size); -} diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 67716d4aae..df6efd8bf2 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,45 +18,41 @@ * Foundation, Inc. */ +#include #include +#include #include #include +#include #include -#include -#include -#include #include +#include #include -#if CONFIG_EC_GOOGLE_CHROMEEC +#include +#include +#include +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) #include +#include #endif #include #include -#include #include +#include #include +#include +#include #include #include +#include #include #include -#include -#include #include #include #include #include -/* The cache-as-ram assembly file calls romstage_main() after setting up - * cache-as-ram. romstage_main() will then call the mainboards's - * mainboard_romstage_entry() function. That function then calls - * romstage_common() below. The reason for the back and forth is to provide - * common entry point from cache-as-ram while still allowing for code sharing. - * Because we can't use global variables the stack is used for allocations -- - * thus the need to call back and forth. */ - -static void *setup_stack_and_mttrs(void); - -static void program_base_addresses(void) +void program_base_addresses(void) { uint32_t reg; const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); @@ -85,8 +82,8 @@ static void program_base_addresses(void) static void spi_init(void) { - u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + void *scs = (void *)(SPI_BASE_ADDRESS + SCS); + void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); uint32_t reg; /* Disable generating SMI when setting WPD bit. */ @@ -100,51 +97,9 @@ static void spi_init(void) write32(bcr, reg); } -/* Entry from cache-as-ram.inc. */ -void * asmlinkage romstage_main(unsigned long bist, - uint32_t tsc_low, uint32_t tsc_hi) -{ - struct romstage_params rp = { - .bist = bist, - .mrc_params = NULL, - }; - - /* Save initial timestamp from bootblock. */ - timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - - program_base_addresses(); - - tco_disable(); - - byt_config_com1_and_enable(); - - console_init(); - - spi_init(); - - set_max_freq(); - - punit_init(); - - gfx_init(); - -#if CONFIG_EC_GOOGLE_CHROMEEC - /* Ensure the EC is in the right mode for recovery */ - google_chromeec_early_init(); -#endif - - /* Call into mainboard. */ - mainboard_romstage_entry(&rp); - - return setup_stack_and_mttrs(); -} - static struct chipset_power_state power_state CAR_GLOBAL; -static void migrate_power_state(void) +static void migrate_power_state(int is_recovery) { struct chipset_power_state *ps_cbmem; struct chipset_power_state *ps_car; @@ -158,9 +113,9 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); -static struct chipset_power_state *fill_power_state(void) +struct chipset_power_state *fill_power_state(void) { struct chipset_power_state *ps = car_get_var_ptr(&power_state); @@ -170,9 +125,11 @@ static struct chipset_power_state *fill_power_state(void) ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); - ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); - ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2)); + ps->prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); + ps->gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + ps->gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)); + + ps->prev_sleep_state = chipset_prev_sleep_state(ps); printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); @@ -180,193 +137,116 @@ static struct chipset_power_state *fill_power_state(void) ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); - + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps; } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -static int chipset_prev_sleep_state(struct chipset_power_state *ps) +int chipset_prev_sleep_state(struct chipset_power_state *ps) { /* Default to S0. */ - int prev_sleep_state = 0; + int prev_sleep_state = SLEEP_STATE_S0; if (ps->pm1_sts & WAK_STS) { switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { - #if CONFIG_HAVE_ACPI_RESUME + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) case SLP_TYP_S3: - prev_sleep_state = 3; + prev_sleep_state = SLEEP_STATE_S3; break; #endif case SLP_TYP_S5: - prev_sleep_state = 5; + prev_sleep_state = SLEEP_STATE_S5; break; } + /* Clear SLP_TYP. */ outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); } - if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { - prev_sleep_state = 5; - } + if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = SLEEP_STATE_S5; return prev_sleep_state; } -/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) -{ - struct romstage_handoff *handoff; - struct chipset_power_state *ps; - int prev_sleep_state; - - timestamp_add_now(TS_BEFORE_INITRAM); - - ps = fill_power_state(); - prev_sleep_state = chipset_prev_sleep_state(ps); - - printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); - -#if CONFIG_ELOG_BOOT_COUNT - if (prev_sleep_state != 3) - boot_count_increment(); -#endif - - - /* Initialize RAM */ - raminit(params->mrc_params, prev_sleep_state); - - timestamp_add_now(TS_AFTER_INITRAM); - - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = (prev_sleep_state == 3); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - - if (CONFIG_LPC_TPM) { - init_tpm(prev_sleep_state == 3); - } -} - -void asmlinkage romstage_after_car(void) -{ - timestamp_add_now(TS_END_ROMSTAGE); - - /* Load the ramstage. */ - copy_and_run(); - while (1); -} - -static inline uint32_t *stack_push(u32 *stack, u32 value) +/* SOC initialization before the console is enabled */ +void soc_pre_console_init(struct romstage_params *params) { - stack = &stack[-1]; - *stack = value; - return stack; + /* Early chipset initialization */ + program_base_addresses(); + tco_disable(); } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -static unsigned long choose_top_of_stack(void) +/* SOC initialization after console is enabled */ +void soc_romstage_init(struct romstage_params *params) { - unsigned long stack_top; - const unsigned long romstage_ram_stack_size = 0x5000; + /* Continue chipset initialization */ + spi_init(); - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Ensure the EC is in the right mode for recovery */ + google_chromeec_early_init(); +#endif } -/* setup_stack_and_mttrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void *setup_stack_and_mttrs(void) +/* SOC initialization after RAM is enabled */ +void soc_after_ram_init(struct romstage_params *params) { - unsigned long top_of_stack; - int num_mtrrs; - uint32_t *slot; - uint32_t mtrr_mask_upper; - uint32_t top_of_ram; - - /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; - slot = (void *)top_of_stack; - num_mtrrs = 0; + u32 value; - /* The upper bits of the MTRR mask need to set according to the number - * of physical address bits. */ - mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; - - /* The order for each MTRR is value then base with upper 32-bits of - * each value coming before the lower 32-bits. The reasoning for - * this ordering is to create a stack layout like the following: - * +0: Number of MTRRs - * +4: MTRR base 0 31:0 - * +8: MTRR base 0 63:32 - * +12: MTRR mask 0 31:0 - * +16: MTRR mask 0 63:32 - * +20: MTRR base 1 31:0 - * +24: MTRR base 1 63:32 - * +28: MTRR mask 1 31:0 - * +32: MTRR mask 1 63:32 - */ - - /* Cache the ROM as WP just below 4GiB. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); - num_mtrrs++; - - /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); - num_mtrrs++; - - top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the - * start of the TSEG region. It is required to be 8MiB aligned. Set - * this area as cacheable so it can be used later for ramstage before - * setting up the entire RAM as cacheable. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); - num_mtrrs++; - - /* Cache 8MiB at the top of ram. Top of ram is where the TSEG - * region resides. However, it is not restricted to SMM mode until - * SMM has been relocated. By setting the region to cacheable it - * provides faster access when relocating the SMM handler as well - * as using the TSEG region for other purposes. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); - num_mtrrs++; - - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. */ - slot = stack_push(slot, num_mtrrs); - - return slot; + /* Make sure that E0000 and F0000 are RAM */ + printk(BIOS_DEBUG, "Disable ROM shadow below 1MB.\n"); + value = iosf_bunit_read(BUNIT_BMISC); + value |= 3; + iosf_bunit_write(BUNIT_BMISC, value); } -void ramstage_cache_invalid(void) +/* Initialize the UPD parameters for MemoryInit */ +void soc_memory_init_params(MEMORY_INIT_UPD *params) { -#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE - /* Perform cold reset on invalid ramstage cache. */ - cold_reset(); -#endif + const struct device *dev; + const struct soc_intel_braswell_config *config; + + /* Set the parameters for MemoryInit */ + dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + config = dev->chip_info; + printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); + params->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->PcdMrcInitTsegSize : 0; + params->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; + params->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; + params->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; + params->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; + params->PcdApertureSize = config->PcdApertureSize; + params->PcdGttSize = config->PcdGttSize; + params->PcdLegacySegDecode = config->PcdLegacySegDecode; } -#if CONFIG_CHROMEOS -int vboot_get_sw_write_protect(void) +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, + MEMORY_INIT_UPD *new) { - u8 status; - /* Return unprotected status if status read fails. */ - return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80)); + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + soc_display_upd_value("PcdMrcInitTsegSize", 2, + old->PcdMrcInitTsegSize, new->PcdMrcInitTsegSize); + soc_display_upd_value("PcdMrcInitMmioSize", 2, + old->PcdMrcInitMmioSize, new->PcdMrcInitMmioSize); + soc_display_upd_value("PcdMrcInitSpdAddr1", 1, + old->PcdMrcInitSpdAddr1, new->PcdMrcInitSpdAddr1); + soc_display_upd_value("PcdMrcInitSpdAddr2", 1, + old->PcdMrcInitSpdAddr2, new->PcdMrcInitSpdAddr2); + soc_display_upd_value("PcdMemChannel0Config", 1, + old->PcdMemChannel0Config, new->PcdMemChannel0Config); + soc_display_upd_value("PcdMemChannel1Config", 1, + old->PcdMemChannel1Config, new->PcdMemChannel1Config); + soc_display_upd_value("PcdMemorySpdPtr", 4, + old->PcdMemorySpdPtr, new->PcdMemorySpdPtr); + soc_display_upd_value("PcdIgdDvmt50PreAlloc", 1, + old->PcdIgdDvmt50PreAlloc, new->PcdIgdDvmt50PreAlloc); + soc_display_upd_value("PcdApertureSize", 1, + old->PcdApertureSize, new->PcdApertureSize); + soc_display_upd_value("PcdGttSize", 1, + old->PcdGttSize, new->PcdGttSize); + soc_display_upd_value("PcdLegacySegDecode", 1, + old->PcdLegacySegDecode, new->PcdLegacySegDecode); } -#endif diff --git a/src/soc/intel/braswell/romstage/uart.c b/src/soc/intel/braswell/romstage/uart.c deleted file mode 100644 index 36776087f1..0000000000 --- a/src/soc/intel/braswell/romstage/uart.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include -#include -#include -#include -#include -#include - -void byt_config_com1_and_enable(void) -{ - uint32_t reg; - - /* Enable the UART hardware for COM1. */ - reg = 1; - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); - - /* Set up the pads to select the UART function */ - score_select_func(UART_RXD_PAD, 1); - score_select_func(UART_TXD_PAD, 1); -} -- cgit v1.2.3