From 056fbe49ff9cccc7646371452431a05b47544057 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 6 Nov 2019 12:07:05 +0200 Subject: ELOG, soc/intel: Avoid some preprocessor use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5378573f37daa4f09db332023027deda677c7aeb Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36646 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/braswell/smm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/braswell/smm.c') diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index 364cda5b5a..c108a3629e 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -39,7 +39,8 @@ void smm_southbridge_clear_state(void) uint32_t smi_en; /* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state(); printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); -- cgit v1.2.3