From 3fa80a9c6f44362e53d33d09da1875a42b98b30f Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Wed, 22 Mar 2017 16:33:36 -0700 Subject: soc/intel/braswell: Put SERIRQ in quiet mode Cherry-pick from Chromium commit 1568761. Original-Change-Id: If459c3cab8fb7ca13d8bff3173a94855ec2e2810 Original-Signed-off-by: Hannah Williams Original-Reviewed-by: Aaron Durbin Original-Tested-by: Kevin K Wong Original-Reviewed-by: Duncan Laurie Original-Tested-by: Aseda Aboagye Change-Id: Ibb2e6d316adcfcc0d56d242501aac9c4c0bbdf62 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/21173 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/braswell/southcluster.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/soc/intel/braswell/southcluster.c') diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 0e2d5e2024..e03312386a 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -38,6 +38,18 @@ #include #include #include +#include + +static const struct reg_script ops[] = { + REG_MMIO_RMW32(ILB_BASE_ADDRESS + SCNT, + ~SCNT_MODE, 0), /* put LPC SERIRQ in Quiet Mode */ + REG_SCRIPT_END +}; + +static void enable_serirq_quiet_mode(void) +{ + reg_script_run(ops); +} static inline void add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) @@ -503,6 +515,7 @@ static void finalize_chipset(void *unused) write32(spi + LVSCC, cfg.lvscc | VCL); } spi_init(); + enable_serirq_quiet_mode(); printk(BIOS_DEBUG, "Finalizing SMM.\n"); outb(APM_CNT_FINALIZE, APM_CNT); -- cgit v1.2.3