From 9dcd4f059b5ba5229c90385e3d384ec04cc734f5 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 17 Aug 2015 18:09:14 -0700 Subject: fsp raminit: Add romstage_params to soc_memory_init_params The SOC handler for memory init params is only taking UPD as an input which does not allow it to use romstage_params. In addition the UPD input is called params which is confusing so rename it to upd so romstage_params can be passed properly. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados p2 Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48 Signed-off-by: Patrick Georgi Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773 Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/294066 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11413 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/braswell/romstage/romstage.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) (limited to 'src/soc/intel/braswell') diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 64a3deee9a..1dbff5478e 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -203,7 +203,8 @@ void soc_after_ram_init(struct romstage_params *params) } /* Initialize the UPD parameters for MemoryInit */ -void soc_memory_init_params(MEMORY_INIT_UPD *params) +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) { const struct device *dev; const struct soc_intel_braswell_config *config; @@ -212,16 +213,16 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params) dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); config = dev->chip_info; printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - params->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0; - params->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; - params->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; - params->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; - params->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; - params->PcdApertureSize = config->PcdApertureSize; - params->PcdGttSize = config->PcdGttSize; - params->PcdLegacySegDecode = config->PcdLegacySegDecode; - params->PcdDvfsEnable = config->PcdDvfsEnable; + upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; + upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; + upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; + upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; + upd->PcdApertureSize = config->PcdApertureSize; + upd->PcdGttSize = config->PcdGttSize; + upd->PcdLegacySegDecode = config->PcdLegacySegDecode; + upd->PcdDvfsEnable = config->PcdDvfsEnable; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, -- cgit v1.2.3