From 5403423656f424fb34854592f0f2da4baeb0615c Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 21 Jun 2020 18:08:53 +0200
Subject: soc/intel/broadwell: Use common early SPI code

Change-Id: Ifd0e8e6d8169a762a4d17839c3fd7b7e5493a344
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
---
 src/soc/intel/broadwell/bootblock/pch.c | 15 ++-------------
 1 file changed, 2 insertions(+), 13 deletions(-)

(limited to 'src/soc/intel/broadwell/bootblock')

diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c
index c7b3e67f1e..27d9a3e8d6 100644
--- a/src/soc/intel/broadwell/bootblock/pch.c
+++ b/src/soc/intel/broadwell/bootblock/pch.c
@@ -10,18 +10,7 @@
 #include <reg_script.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
-
-/*
- * Enable Prefetching and Caching.
- */
-static void enable_spi_prefetch(void)
-{
-	u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc);
-	reg8 &= ~(3 << 2);
-	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
-	pci_write_config8(PCH_DEV_LPC, 0xdc, reg8);
-}
-
+#include <southbridge/intel/common/early_spi.h>
 
 static void map_rcba(void)
 {
@@ -105,7 +94,7 @@ static void pch_early_lpc(void)
 void bootblock_early_southbridge_init(void)
 {
 	map_rcba();
-	enable_spi_prefetch();
+	enable_spi_prefetching_and_caching();
 	enable_port80_on_lpc();
 	set_spi_speed();
 	pch_early_lpc();
-- 
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