From a6354a1acadc7825364c6a6e7fd3b24a405a62a1 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Fri, 26 Dec 2014 22:11:14 -0700 Subject: broadwell: Preparations for building Updated Intel Broadwell for differences in the source based on the chromium tree. It is missing most of the recent updates on coreboot.org. - makefile changes for Elog and IDF tool - kconfig changes for ME, ucode, and other updates - update oprom flag - update timestamp mechanism - cbfs payload function is now generic Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe Signed-off-by: Marc Jones Reviewed-on: http://review.coreboot.org/7939 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/soc/intel/broadwell/bootblock/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/broadwell/bootblock') diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index da7b99df62..e20ced2cf6 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -48,7 +48,7 @@ static void enable_rom_caching(void) disable_cache(); /* Why only top 4MiB ? */ - set_var_mtrr(1, CACHE_ROM_BASE, CONFIG_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); + set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); enable_cache(); /* Enable Variable MTRRs */ -- cgit v1.2.3