From de7ed6fc7cdb3f55894e613bdc0c394fa8f57494 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 7 Dec 2014 14:58:18 -0700 Subject: intel/broadwell: Spelling fixes Change-Id: I2f970c6970b4996fcefbde89332210f5a1afe836 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/7702 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/soc/intel/broadwell/bootblock/pch.c | 2 +- src/soc/intel/broadwell/bootblock/systemagent.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/broadwell/bootblock') diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index 9e76f7976f..2475a25955 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -55,7 +55,7 @@ static void map_rcba(void) static void enable_port80_on_lpc(void) { - /* Enable port 80 POST on LPC. The chipset does this by deafult, + /* Enable port 80 POST on LPC. The chipset does this by default, * but it doesn't appear to hurt anything. */ u32 gcs = RCBA32(GCS); gcs = gcs & ~0x4; diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index b2dd27b1a1..b5f82b21b4 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -32,7 +32,7 @@ static void bootblock_northbridge_init(void) * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. -- cgit v1.2.3