From 3ed4d39b5727587913f6c872772cefbd2d106c07 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 31 Jul 2014 10:41:56 -0700 Subject: broadwell: Add config option to disable DSP power gating in D3 This is useful for debug and testing. BUG=chrome-os-partner:29649 BRANCH=None TEST=build and boot on samus Original-Change-Id: I9050e75fd7c308ebd97d196298c687f8b0f8f97d Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/210599 Original-Reviewed-by: Aaron Durbin (cherry picked from commit 2831154af4f33717489cb0b62aef228fb8f7c2e2) Signed-off-by: Marc Jones Change-Id: Ie622df02d9ab219cefce5f11332e010b47e3ec6e Reviewed-on: http://review.coreboot.org/8947 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/chip.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/broadwell/chip.h') diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index a3b716b3bc..e433483198 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -84,6 +84,9 @@ struct soc_intel_broadwell_config { uint8_t sio_i2c0_voltage; uint8_t sio_i2c1_voltage; + /* Disable ADSP power gating in D3 */ + uint8_t adsp_d3_pg_disable; + /* * Clock Disable Map: * [21:16] = CLKOUT_PCIE# 5-0 -- cgit v1.2.3