From 49ee5efea72c5198034a1991491b11facd377653 Mon Sep 17 00:00:00 2001 From: Georg Wicherski Date: Tue, 13 Oct 2015 16:27:15 +0200 Subject: soc/intel/broadwell: fix USBDEBUG copy-pasta MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The broadwell soc code was upstreamed based off an old coreboot branch and apparently never tested with USBDEBUG. This changeset fixes USBDEBUG on the not yet upstreamed Auron-Paine board, as verified with a FT232H setup. The fix is simply removing outdated code that since branching off had been deduplicated in upstream coreboot, anyway. Change-Id: I53c924aa2a5357ed8313d0c9eaa2f9f9e132345e Signed-off-by: Georg Wicherski Reviewed-on: http://review.coreboot.org/11874 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Stefan Reinauer Reviewed-by: Alexandru Gagniuc --- src/soc/intel/broadwell/cpu.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'src/soc/intel/broadwell/cpu.c') diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index f3ab30abbf..2580ef9823 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -574,27 +574,13 @@ static void configure_mca(void) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } -#if CONFIG_USBDEBUG -static unsigned ehci_debug_addr; -#endif - static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { -#if CONFIG_USBDEBUG - if(!ehci_debug_addr) - ehci_debug_addr = get_ehci_debug(); - set_ehci_debug(0); -#endif - /* Setup MTRRs based on physical address size. */ x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); x86_mtrr_check(); -#if CONFIG_USBDEBUG - set_ehci_debug(ehci_debug_addr); -#endif - initialize_vr_config(); calibrate_24mhz_bclk(); configure_pch_power_sharing(); -- cgit v1.2.3