From 1500dd081b386db9b03ff78e74831cf6c9f88ba7 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 26 Oct 2020 00:32:42 +0100 Subject: soc/intel/broadwell: Flatten northbridge folder structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Having folders for bootblock and romstage is no longer necessary. Change-Id: I7d1f4063de6a1a1ff9ee7478e94f889a50102054 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46795 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/early_init.c | 58 ++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 src/soc/intel/broadwell/early_init.c (limited to 'src/soc/intel/broadwell/early_init.c') diff --git a/src/soc/intel/broadwell/early_init.c b/src/soc/intel/broadwell/early_init.c new file mode 100644 index 0000000000..6bf7ba7a59 --- /dev/null +++ b/src/soc/intel/broadwell/early_init.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static void broadwell_setup_bars(void) +{ + /* Set up all hardcoded northbridge BARs */ + pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1); + pci_write_config32(SA_DEV_ROOT, DMIBAR, DMI_BASE_ADDRESS | 1); + pci_write_config32(SA_DEV_ROOT, EPBAR, EP_BASE_ADDRESS | 1); + + MCHBAR32(EDRAMBAR) = EDRAM_BASE_ADDRESS | 1; + MCHBAR32(GDXCBAR) = GDXC_BASE_ADDRESS | 1; + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + pci_write_config8(SA_DEV_ROOT, PAM0, 0x30); + pci_write_config8(SA_DEV_ROOT, PAM1, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM2, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM3, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM4, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM5, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM6, 0x33); +} + +void systemagent_early_init(void) +{ + const bool vtd_capable = + !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); + + broadwell_setup_bars(); + + /* Device enable: IGD and Mini-HD */ + pci_write_config32(SA_DEV_ROOT, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); + + if (vtd_capable) { + /* setup BARs: zeroize top 32 bits; set enable bit */ + MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32; + MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1; + MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32; + MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1; + + /* set PRSCAPDIS, lock GFXVTBAR policy cfg registers */ + u32 reg32; + reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS)); + write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), + reg32 | DMAR_LCKDN | PRSCAPDIS); + /* lock VTVC0BAR policy cfg registers */ + reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)); + write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS), + reg32 | DMAR_LCKDN); + } +} -- cgit v1.2.3