From 26a682c9441b4f7312ff9f69d22029841aa245bd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Fri, 2 Aug 2019 06:13:22 +0300
Subject: intel/baytrail,broadwell: Move stage cache support function
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.

Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/broadwell/memmap.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

(limited to 'src/soc/intel/broadwell/memmap.c')

diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index 836fda8b5d..7c53fa6468 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -15,11 +15,14 @@
 
 #define __SIMPLE_DEVICE__
 
-#include <device/pci_ops.h>
 #include <cbmem.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/systemagent.h>
+#include <soc/smm.h>
+#include <stage_cache.h>
+#include <stdint.h>
 
 static uintptr_t dpr_region_start(void)
 {
@@ -42,3 +45,15 @@ void *cbmem_top(void)
 {
 	return (void *) dpr_region_start();
 }
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+	/* The ramstage cache lives in the TSEG region.
+	 * The top of RAM is defined to be the TSEG base address. */
+	u32 offset = smm_region_size();
+	offset -= CONFIG_IED_REGION_SIZE;
+	offset -= CONFIG_SMM_RESERVED_SIZE;
+
+	*base = (void *)(cbmem_top() + offset);
+	*size = CONFIG_SMM_RESERVED_SIZE;
+}
-- 
cgit v1.2.3