From 26a682c9441b4f7312ff9f69d22029841aa245bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 2 Aug 2019 06:13:22 +0300 Subject: intel/baytrail,broadwell: Move stage cache support function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let garbage-collection take care of stage_cache_external_region() when it is not needed and move implementation to a suitable file already building for needed stages. Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/Makefile.inc | 3 --- src/soc/intel/broadwell/memmap.c | 17 ++++++++++++++++- src/soc/intel/broadwell/stage_cache.c | 31 ------------------------------- 3 files changed, 16 insertions(+), 35 deletions(-) delete mode 100644 src/soc/intel/broadwell/stage_cache.c (limited to 'src/soc/intel/broadwell') diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index a79fa464a9..91a3da02c6 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -68,9 +68,6 @@ romstage-y += spi.c postcar-y += spi.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-y += stage_cache.c -romstage-y += stage_cache.c -postcar-y += stage_cache.c ramstage-y += systemagent.c bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 836fda8b5d..7c53fa6468 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -15,11 +15,14 @@ #define __SIMPLE_DEVICE__ -#include #include #include +#include #include #include +#include +#include +#include static uintptr_t dpr_region_start(void) { @@ -42,3 +45,15 @@ void *cbmem_top(void) { return (void *) dpr_region_start(); } + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + u32 offset = smm_region_size(); + offset -= CONFIG_IED_REGION_SIZE; + offset -= CONFIG_SMM_RESERVED_SIZE; + + *base = (void *)(cbmem_top() + offset); + *size = CONFIG_SMM_RESERVED_SIZE; +} diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c deleted file mode 100644 index dc59ab7756..0000000000 --- a/src/soc/intel/broadwell/stage_cache.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The ramstage cache lives in the TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - u32 offset = smm_region_size(); - offset -= CONFIG_IED_REGION_SIZE; - offset -= CONFIG_SMM_RESERVED_SIZE; - - *base = (void *)(cbmem_top() + offset); - *size = CONFIG_SMM_RESERVED_SIZE; -} -- cgit v1.2.3