From 73b1bd7992fb33f33c33747fd0919fc495c3d5c4 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Thu, 28 Nov 2019 13:56:24 +0530
Subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock

This patch performs below operations:
1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration
2. Move soc_gpio_pm_configuration() to gpio_common.c
3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration
is updated with devicetree.cb value even with platform reset.

BUG=b:144002424
TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb

Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/intel/cannonlake/bootblock/pch.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/intel/cannonlake/bootblock/pch.c')

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 39433a26d9..9ad7e86178 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -28,6 +28,7 @@
 #include <intelblocks/smbus.h>
 #include <intelblocks/tco.h>
 #include <soc/bootblock.h>
+#include <soc/gpio.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <soc/p2sb.h>
@@ -198,4 +199,7 @@ void pch_early_init(void)
 	pmc_gpe_init();
 
 	enable_rtc_upper_bank();
+
+	/* GPIO community PM configuration */
+	soc_gpio_pm_configuration();
 }
-- 
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