From 95b61752dbb56b9a7a2da439c5d21e30643661ef Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Wed, 4 Oct 2017 23:08:40 -0700 Subject: soc/intel/cannonlake: Add support for C state and P state This patch adds the C state and P state configurations for cannonlake soc. TEST = Boot and test the CPU states for all the cores are present in "powertop" tool output. Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/21891 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/chip.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/cannonlake/chip.c') diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 23e6fffbe8..2810ed11f5 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -154,6 +154,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, + .acpi_fill_ssdt_generator = generate_cpu_entries, }; static void soc_enable(device_t dev) -- cgit v1.2.3