From a0729899d7aa2764b83ba7b8c00fe36a4bb3fb2e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 30 Sep 2018 01:39:49 +0530 Subject: soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices This patch provides option for PCI IRQ mapping in both PIC and APIC mode. TEST=Build and Boot on CNL RVP. Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/28799 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/include/soc/irq.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/cannonlake/include') diff --git a/src/soc/intel/cannonlake/include/soc/irq.h b/src/soc/intel/cannonlake/include/soc/irq.h index 5b6715fceb..61f4025811 100644 --- a/src/soc/intel/cannonlake/include/soc/irq.h +++ b/src/soc/intel/cannonlake/include/soc/irq.h @@ -87,8 +87,9 @@ #define XHCI_IRQ 16 #define OTG_IRQ 17 -#define THRMAL_IRQ 16 -#define CNViWIFI_IRQ 16 +#define PMC_SRAM_IRQ 18 +#define THERMAL_IRQ 16 +#define CNViWIFI_IRQ 19 #define UFS_IRQ 16 #define CIO_INTA_IRQ 16 #define CIO_INTD_IRQ 19 @@ -101,6 +102,6 @@ #define IGFX_IRQ 16 #define SA_THERMAL_IRQ 16 -#define SKYCAM_IRQ 16 -#define GMM_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 #endif /* _SOC_IRQ_H_ */ -- cgit v1.2.3