From 1159a163cd36318d27f8f3b71617ad4a5b781efb Mon Sep 17 00:00:00 2001 From: John Zhao Date: Mon, 22 Apr 2019 10:45:51 -0700 Subject: soc/intel/cnl: Enable VT-d Enable VT-d through fsp upd VtdDisable. Update remapping structure types in numerical order as all remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. BUG=b:130351429 TEST=Booted to kernel and verified the DMAR table contents. Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Pratikkumar V Prajapati --- src/soc/intel/cannonlake/systemagent.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'src/soc/intel/cannonlake/systemagent.c') diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index d850b15b34..3f01f14dcf 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -33,8 +33,6 @@ */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { - const struct soc_intel_cannonlake_config *const config = dev->chip_info; - static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, @@ -63,10 +61,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) return; - if (!(config && config->VtdDisable)) { - sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, ARRAY_SIZE(soc_vtd_resources)); - } } /* -- cgit v1.2.3