From aa3d78d5e695f983ace43a594191f31769cd410c Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 8 Aug 2017 11:32:35 -0700 Subject: soc/intel/cannonlake: Add ramstage SystemAgent support Revere memory resource within SA, also perform necessary routine for initialization during ramstage. Change-Id: Ibaa7334b0d94fedc87e707a136c9537e2e6f57cb Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/20914 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/systemagent.c | 58 ++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 src/soc/intel/cannonlake/systemagent.c (limited to 'src/soc/intel/cannonlake/systemagent.c') diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c new file mode 100644 index 0000000000..7ce152dc21 --- /dev/null +++ b/src/soc/intel/cannonlake/systemagent.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +/* + * SoC implementation + * + * Add all known fixed memory ranges for Host Controller/Mmeory + * controller. + */ +void soc_add_fixed_mmio_resources(struct device *dev, int *index) +{ + static const struct sa_mmio_descriptor soc_fixed_resources[] = { + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + "PCIEXBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, + ARRAY_SIZE(soc_fixed_resources)); +} + +/* + * SoC implementation + * + * Perform System Agent Initialization during Ramstage phase. + */ +void soc_systemagent_init(struct device *dev) +{ + /* Enable Power Aware Interrupt Routing */ + enable_power_aware_intr(); + + /* Enable BIOS Reset CPL */ + enable_bios_reset_cpl(); +} -- cgit v1.2.3