From dadcbfbe8c682c89b277fdbdfdd26cabd15fc20a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 4 Oct 2020 14:48:05 +0200 Subject: soc/intel: convert XTAL frequency constant to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/Kconfig | 3 +++ src/soc/intel/cannonlake/cpu.c | 11 +++++++---- src/soc/intel/cannonlake/include/soc/cpu.h | 3 --- 3 files changed, 10 insertions(+), 7 deletions(-) (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dc2be28f81..24f64b1887 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -245,6 +245,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 24000000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 216 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index ddedb3fed2..0622034217 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -114,19 +114,22 @@ static void enable_pm_timer_emulation(void) { msr_t msr; + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); } + static void set_energy_perf_bias(u8 policy) { msr_t msr; diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index b356d3a9b8..3542a2b8a4 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -22,9 +22,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 24MHz. */ -#define CTC_FREQ 24000000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ -- cgit v1.2.3