From f212cf3506a9ad3d699a4afe148bfd554932f7b8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 18 Dec 2018 10:24:55 +0100 Subject: soc/intel: Standardize names of common MSRs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use defined name in Intel 64 and IA-32 Architectures Software Developer’s Manual. Renamed MSRs are (register address, register name): 0x35 MSR_CORE_THREAD_COUNT 0x121 MSR_EMULATE_PM_TIMER 0x1f4 MSR_PRMRR_PHYS_BASE 0x1f5 MSR_PRMRR_PHYS_MASK 0x2f4 MSR_UNCORE_PRMRR_PHYS_BASE 0x2f5 MSR_UNCORE_PRMRR_PHYS_MASK Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/30288 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/soc/intel/cannonlake/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index fe34d05060..96018637c1 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -185,7 +185,7 @@ static void enable_pm_timer_emulation(void) /* Set PM1 timer IO port and enable*/ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TMR, msr); + wrmsr(MSR_EMULATE_PM_TIMER, msr); } /* All CPUs including BSP will run the following function. */ -- cgit v1.2.3