From f95b4a708e021f4eb3cb36aa1f3bc6a2076f2f6b Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 29 Oct 2018 16:48:02 -0700 Subject: soc/intel: Enable GPIO functions in verstage Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. Change-Id: Icd4344c4d66dbe21fda9dc27e61a836c1dd9be07 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/29407 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index e95d04f274..2452f5066b 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -77,11 +77,13 @@ bootblock-y += gpio_cnp_h.c romstage-y += gpio_cnp_h.c ramstage-y += gpio_cnp_h.c smm-y += gpio_cnp_h.c +verstage-y += gpio_cnp_h.c else bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c smm-y += gpio.c +verstage-y += gpio.c endif CPPFLAGS_common += -I$(src)/soc/intel/cannonlake -- cgit v1.2.3