From 3e5bc1feabd58f1d6f37f8b50156778caa00bfea Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Wed, 24 Jun 2015 11:17:54 -0700 Subject: soc/intel/common: Restrict common romstage/ramstage code to FSP Restrict the use of the common romstage/ramstage code to FSP 1.1 BRANCH=none BUG=None TEST=Build and run on cyan/sklrvp Change-Id: Ifbdb6b4c201560a97617e83d69bf9974f9411994 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/10653 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/common/Kconfig') diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 75e585d70a..3d0c0eff78 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -73,18 +73,22 @@ config SOC_INTEL_COMMON_FSP_RAM_INIT config SOC_INTEL_COMMON_FSP_ROMSTAGE bool default n + depends on PLATFORM_USES_FSP1_1 config SOC_INTEL_COMMON_RESET bool default n + depends on PLATFORM_USES_FSP1_1 config SOC_INTEL_COMMON_STACK bool default n + depends on PLATFORM_USES_FSP1_1 config SOC_INTEL_COMMON_STAGE_CACHE bool default n + depends on PLATFORM_USES_FSP1_1 config ROMSTAGE_RAM_STACK_SIZE hex "Size of the romstage RAM stack in bytes" -- cgit v1.2.3