From 9d9a121fa0cc0a5b303aaf377ce2a8e426ef0d3a Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 19 Apr 2017 10:02:27 -0500 Subject: soc/intel/common: provide default tis_plat_irq_status() implementation On Intel platforms utilizing the CR50 TPM the interrupts are routed to GPIOs connected to the GPE blocks. Therefore, provide a common implementation for tis_plat_irq_status() to reduce code duplication. This code could be further extended to not be added based on MAINBOARD_HAS_TPM_CR50, but that's all that's using it for now. Change-Id: I955df0a536408b2ccd07146893337c53799e243f Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/19369 Reviewed-by: Furquan Shaikh Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/soc/intel/common/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/common/Kconfig') diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 919cb50406..7612850965 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -130,4 +130,10 @@ config SOC_INTEL_COMMON_NHLT bool default n +config TPM_TIS_ACPI_INTERRUPT + int + help + acpi_get_gpe() is used to provide interrupt status to TPM layer. + This option specifies the GPE number. + endif # SOC_INTEL_COMMON -- cgit v1.2.3