From aedbfc8f0917b332e648fe6c4333567bd8e58b0d Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 24 Oct 2016 15:23:40 -0700 Subject: soc/intel/common: Enable support to write protect SPI flash range Write-protect SPI flash range provided by caller by using a free Flash Protected Range (FPR) register. This expects SoC to define a callback for providing information about the first FPR register address and maximum number of FPRs supported. BUG=chrome-os-partner:58896 Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/17115 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/common/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/common/Kconfig') diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 8eae23b6e7..affec55718 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -9,6 +9,10 @@ config CACHE_MRC_SETTINGS bool "Save cached MRC settings" default n +config SOC_INTEL_COMMON_SPI_PROTECT + bool + default n + if CACHE_MRC_SETTINGS config MRC_SETTINGS_CACHE_BASE -- cgit v1.2.3