From 0946ec37aa4660ecf16d66cb1174a68df0afc4f0 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Mon, 20 Apr 2015 15:24:54 -0700 Subject: Intel Common SOC: Add romstage support Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/Makefile.inc | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/common/Makefile.inc') diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 6d40aa7037..76854ad857 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,10 +1,19 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RAM_INIT) += raminit.c +romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_ROMSTAGE) += romstage.c +romstage-$(CONFIG_SOC_INTEL_COMMON_STACK) += stack.c +romstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c + +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_ramstage.c ramstage-y += hda_verb.c -ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c -romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c +ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c endif -- cgit v1.2.3