From 8adaffcbed6372970f34b85177bd42bb508d03e2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 10 Aug 2019 21:43:12 +0530 Subject: soc/intel/common: Fix typo mistake in cache_as_ram.S Change-Id: I14c0e87012bdbaaff50844ed097b66e2221b1e08 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34818 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: V Sowmya --- src/soc/intel/common/block/cpu/car/cache_as_ram.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/common/block/cpu') diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index b1648e8eed..d5f5081c3c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -365,7 +365,7 @@ find_llc_subleaf: jnz find_llc_subleaf /* - * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * Set MSR 0xC91 IA32_L3_MASK_1 = 0xE/0xFE/0xFFE/0xFFFE * for 4/8/16 way of LLC */ shr $22, %ebx -- cgit v1.2.3