From 0946ec37aa4660ecf16d66cb1174a68df0afc4f0 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Mon, 20 Apr 2015 15:24:54 -0700 Subject: Intel Common SOC: Add romstage support Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/hda_verb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/common/hda_verb.c') diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index c4cdb3d70c..ecd6c810b8 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -72,7 +72,7 @@ int hda_codec_detect(u8 *base) /* Clear the "State Change Status Register" STATESTS bits * for each of the "SDIN Stat Change Status Flag" - */ + */ write8(base + HDA_STATESTS_REG, 0xf); /* Turn off the link and poll RESET# bit until it reads back as 0 */ -- cgit v1.2.3