From e6af4be1587f34f2f79d6e8b9ece94cfa7cd4c8e Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 24 Sep 2015 12:26:31 -0500 Subject: intel fsp1_1: prepare for romstage vboot verification split In order to introduce a verstage which performs vboot verification the cache-as-ram environment needs to be generalized and split into pieces that can be utilized in romstage and/or verstage. Therefore, the romstage pieces were removed from the cache-as-ram specific pieces that are generic: - Add fsp/car.h to house the declarations for functions in the cache-as-ram environment - Only have cache_as_ram_params which are isolated form the cache-as-ram environment aside from FSP_INFO_HEADER. - Hardware requirements for console initialization is done in the cache-as-ram specific files. - Provide after_raminit.S which can be included from a romstage separated from cache-as-ram as well as one that is tightly coupled to the cache-as-ram environment. - Update the fallout from the API changes in soc/intel/{braswell,common,skylake}. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/302481 Original-Reviewed-by: Duncan Laurie Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11816 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/common/romstage.c | 73 +++++------------------------------------ 1 file changed, 9 insertions(+), 64 deletions(-) (limited to 'src/soc/intel/common/romstage.c') diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c index 42e624cab9..6fc569c39a 100644 --- a/src/soc/intel/common/romstage.c +++ b/src/soc/intel/common/romstage.c @@ -48,37 +48,22 @@ #include #include -/* Entry from cache-as-ram.inc. */ -asmlinkage void *romstage_main(struct cache_as_ram_params *car_params) +asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) { void *top_of_stack; struct pei_data pei_data; - struct fsp_car_context *fsp_car_context; struct romstage_params params = { - .bist = car_params->bist, .pei_data = &pei_data, - .chipset_context = car_params->chipset_context, + .chipset_context = fih, }; - fsp_car_context = car_params->chipset_context; post_code(0x30); - /* Save timestamp data */ - timestamp_init(car_params->tsc); timestamp_add_now(TS_START_ROMSTAGE); memset(&pei_data, 0, sizeof(pei_data)); - /* Call into pre-console init code. */ - soc_pre_console_init(); - mainboard_pre_console_init(); - - /* Start console drivers */ - console_init(); - /* Display parameters */ - printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); - printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", CONFIG_MMCONF_BASE_ADDRESS); printk(BIOS_INFO, "Using: %s\n", @@ -87,25 +72,11 @@ asmlinkage void *romstage_main(struct cache_as_ram_params *car_params) "No Memory Support")); /* Display FSP banner */ - printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); - print_fsp_info(fsp_car_context->fih); - - if (fsp_car_context->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || - fsp_car_context->bootloader_car_end != - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { - printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n", - CONFIG_DCACHE_RAM_BASE, - CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE, - (long)fsp_car_context->bootloader_car_start, - (long)fsp_car_context->bootloader_car_end); - } + print_fsp_info(fih); /* Get power state */ params.power_state = fill_power_state(); - /* Perform SOC specific initialization. */ - soc_romstage_init(¶ms); - /* * Read and print board version. Done after SOC romstage * in case PCH needs to be configured to talk to the EC. @@ -125,6 +96,11 @@ asmlinkage void *romstage_main(struct cache_as_ram_params *car_params) return top_of_stack; } +void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) +{ + return romstage_main(fih); +} + /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -204,13 +180,8 @@ void romstage_common(struct romstage_params *params) init_tpm(params->power_state->prev_sleep_state == SLEEP_STATE_S3); } -asmlinkage void romstage_after_car(void *chipset_context) +void after_cache_as_ram_stage(void) { - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); - printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); - soc_after_temp_ram_exit(); - soc_display_mtrrs(); - /* Load the ramstage. */ copy_and_run(); die("ERROR - Failed to load ramstage!"); @@ -238,11 +209,6 @@ __attribute__((weak)) void mainboard_check_ec_image( #endif } -/* Board initialization before the console is enabled */ -__attribute__((weak)) void mainboard_pre_console_init(void) -{ -} - /* Board initialization before and after RAM is enabled */ __attribute__((weak)) void mainboard_romstage_entry( struct romstage_params *params) @@ -443,29 +409,8 @@ __attribute__((weak)) void soc_after_ram_init(struct romstage_params *params) printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } -/* SOC initialization after temporary RAM is disabled */ -__attribute__((weak)) void soc_after_temp_ram_exit(void) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} - -/* SOC initialization before the console is enabled */ -__attribute__((weak)) void soc_pre_console_init(void) -{ -} - /* SOC initialization before RAM is enabled */ __attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* SOC initialization after console is enabled */ -__attribute__((weak)) void soc_romstage_init(struct romstage_params *params) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) - /* Ensure the EC is in the right mode for recovery */ - google_chromeec_early_init(); -#endif -} -- cgit v1.2.3