From 18d315910adddec70d69fc1cc97426e5bbe9dd5a Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Tue, 7 Jul 2020 16:57:15 +0200 Subject: soc/intel/common/block/pcie: Select ASPM on mainboard basis Current the common soc code automatically selects PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE which breaks booting Windows with a PCIE NVIDIA graphics card attached on mainboards that do not have a CLKREQ# signal. This is commonly used on server and workstations boards where the additional power savings of L1 substate are not required. Make the PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE default y but do not select it anymore by the soc code, thus we can disable it in the mainboard code. Tested on CFL with Windows 10. Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/41696 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/pcie/Kconfig | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig index aa32324401..9c42af6c25 100644 --- a/src/soc/intel/common/block/pcie/Kconfig +++ b/src/soc/intel/common/block/pcie/Kconfig @@ -1,12 +1,20 @@ config SOC_INTEL_COMMON_BLOCK_PCIE bool select PCIEXP_ASPM - select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK - select PCIEXP_L1_SUB_STATE help Intel Processor common PCIE support +if SOC_INTEL_COMMON_BLOCK_PCIE + +config PCIEXP_CLK_PM + default y + +config PCIEXP_L1_SUB_STATE + default y + +endif # SOC_INTEL_COMMON_BLOCK_PCIE + config PCIE_DEBUG_INFO bool help -- cgit v1.2.3