From ed21df6cec49f2c7dd5ae8286eaee958104e781d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= <foss@mniewoehner.de>
Date: Sat, 19 Sep 2020 00:08:45 +0200
Subject: soc/intel/common/block: add code for ACPI CPPC entries generation
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Copy the code for CPPC entries generation, needed for Intel SpeedShift,
from SKL to common ACPI code.

SKL is going to use common ACPI code, too, in the future, so this code
duplication will vanish soon.

Test: dumped SSDT from Clevo L140CU and checked decompiled version after
enabling CPPC entries via Kconfig

Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45535
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/acpi/acpi.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

(limited to 'src/soc/intel/common')

diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 5951b30e11..f0ff89889a 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <acpi/acpigen.h>
+#include <arch/cpu.h>
 #include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
 #include <bootstate.h>
@@ -9,6 +10,7 @@
 #include <acpi/acpi_gnvs.h>
 #include <console/console.h>
 #include <cpu/intel/turbo.h>
+#include <cpu/intel/common/common.h>
 #include <cpu/x86/smm.h>
 #include <intelblocks/acpi.h>
 #include <intelblocks/msr.h>
@@ -20,6 +22,8 @@
 #include <soc/pm.h>
 #include <string.h>
 
+#define  CPUID_6_EAX_ISST	(1 << 7)
+
 __attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
@@ -391,6 +395,23 @@ void generate_t_state_entries(int core, int cores_per_package)
 	acpigen_write_TSS_package(entries, soc_tss_table);
 }
 
+static void generate_cppc_entries(int core_id)
+{
+	if (!(CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) &&
+	      cpuid_eax(6) & CPUID_6_EAX_ISST))
+		return;
+
+	/* Generate GCPC package in first logical core */
+	if (core_id == 0) {
+		struct cppc_config cppc_config;
+		cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2);
+		acpigen_write_CPPC_package(&cppc_config);
+	}
+
+	/* Write _CPC entry for each logical core */
+	acpigen_write_CPPC_method();
+}
+
 __weak void soc_power_states_generation(int core_id,
 						int cores_per_package)
 {
@@ -421,6 +442,8 @@ void generate_cpu_entries(const struct device *device)
 			/* Generate C-state tables */
 			generate_c_state_entries();
 
+			generate_cppc_entries(core_id);
+
 			/* Soc specific power states generation */
 			soc_power_states_generation(core_id, cores_per_package);
 
-- 
cgit v1.2.3