From 1799011dc6914927d951cc076a405c6b20ead5d5 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 27 Aug 2019 11:01:33 +0530 Subject: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code This patch includes common romstage code to setup the console and load postcar. Fix booting regression issue on all latest IA-SOC introduced by CB:34893 Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/35109 Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar Reviewed-by: Maulik V Vaghela Reviewed-by: Furquan Shaikh --- src/soc/intel/denverton_ns/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/denverton_ns/Makefile.inc') diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index f01fadbdfe..10bb665bd0 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -36,6 +36,7 @@ postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c romstage-y += memmap.c romstage-y += reset.c +romstage-y += ../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += tsc_freq.c romstage-y += gpio_dnv.c -- cgit v1.2.3