From b4905625eb863b0d3263ec3e2ea3dfe61d11d49d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 12 Jul 2019 08:02:35 +0300 Subject: soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id375999adad71d95d4968398e90bc3c07f65ea83 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34254 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/romstage.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'src/soc/intel/denverton_ns') diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 6d8eaab9b1..2ad78a02df 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -141,12 +141,9 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; uintptr_t top_of_ram; - -#if CONFIG(HAVE_SMI_HANDLER) void *smm_base; size_t smm_size; uintptr_t tseg_base; -#endif console_init(); @@ -177,7 +174,6 @@ asmlinkage void car_stage_entry(void) /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); -#if CONFIG(HAVE_SMI_HANDLER) /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. @@ -185,10 +181,11 @@ asmlinkage void car_stage_entry(void) * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) { + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + } run_postcar_phase(&pcf); } -- cgit v1.2.3