From b369dde9b1cc9daffce83dc809101e0fd0a0e346 Mon Sep 17 00:00:00 2001
From: "Tan, Lean Sheng" <lean.sheng.tan@intel.com>
Date: Thu, 3 Sep 2020 07:01:09 -0700
Subject: soc/intel/elkhartlake: Update PMC related register definitions

Update ABase, PMC GPIO value sets and PMC register base address.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Iba43b791cab0665ddebfbed68b7e2d15406ad206
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
 src/soc/intel/elkhartlake/bootblock/pch.c   |  2 +-
 src/soc/intel/elkhartlake/include/soc/pmc.h | 28 ++++++++++++++++------------
 2 files changed, 17 insertions(+), 13 deletions(-)

(limited to 'src/soc/intel/elkhartlake')

diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c
index 3988cab3e0..9224c486ec 100644
--- a/src/soc/intel/elkhartlake/bootblock/pch.c
+++ b/src/soc/intel/elkhartlake/bootblock/pch.c
@@ -21,7 +21,7 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0xA00
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x0C00
 
 #define PCR_PSFX_TO_SHDW_BAR0	0
 #define PCR_PSFX_TO_SHDW_BAR1	0x4
diff --git a/src/soc/intel/elkhartlake/include/soc/pmc.h b/src/soc/intel/elkhartlake/include/soc/pmc.h
index 59bee8f4a3..9e6d22f11c 100644
--- a/src/soc/intel/elkhartlake/include/soc/pmc.h
+++ b/src/soc/intel/elkhartlake/include/soc/pmc.h
@@ -5,7 +5,7 @@
 
 /* PCI Configuration Space (D31:F2): PMC */
 #define  PWRMBASE		0x10
-#define  ABASE			0x20
+#define  ABASE			0x40
 
 /* Memory mapped IO registers in PMC */
 #define GEN_PMCON_A			0x1020
@@ -102,17 +102,21 @@
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))
 
-#define  PMC_GPP_G			0x0
-#define  PMC_GPP_B			0x1
-#define  PMC_GPP_A			0x2
-#define  PMC_GPP_R			0x3
-#define  PMC_GPP_S			0x4
-#define  PMC_GPD			0x5
-#define  PMC_GPP_H			0x6
-#define  PMC_GPP_D			0x7
-#define  PMC_GPP_F			0x8
-#define  PMC_GPP_C			0xA
-#define  PMC_GPP_E			0xB
+#define PMC_GPP_B				0x0
+#define PMC_GPP_T				0x1
+#define PMC_GPP_D				0x2
+#define PMC_GPP_A				0x3
+#define PMC_GPP_R				0x4
+#define PMC_GPP_V				0x5
+#define PMC_GPD					0x6
+#define PMC_GPP_H				0x7
+#define PMC_GPP_U				0x8
+#define PMC_VGPIO				0x9
+#define PMC_GPP_F				0xA
+#define PMC_GPP_C				0xB
+#define PMC_GPP_E				0xC
+#define PMC_GPP_G				0xD
+#define PMC_GPP_S				0xE
 
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)
-- 
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