From b5a374d58befa96f718d0c2cee9afafb60867f18 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Tue, 10 Feb 2015 10:16:12 +0100 Subject: fsp_baytrail: Add new microcode for Bay Trail M Add a new microcode for Bay Trail M D0 stepping used in cpu N2807 silicon. In addition, a selection of the used CPU type has been added (I or M/D) which allows to use only the really needed microcode for a given CPU type. Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0 Signed-off-by: Werner Zeh Reviewed-on: http://review.coreboot.org/8399 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/fsp_baytrail/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/fsp_baytrail/Kconfig') diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 87839c40b4..d97879fc5d 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -50,6 +50,10 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select ROMSTAGE_RTC_INIT +config SOC_INTEL_FSP_BAYTRAIL_MD + bool + default n + config BOOTBLOCK_CPU_INIT string default "soc/intel/fsp_baytrail/bootblock/bootblock.c" -- cgit v1.2.3