From 1c3b1112fa2dbdd66b0470224715dc6da254ce62 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Fri, 19 Feb 2016 10:50:38 +0100 Subject: fsp_baytrail: Fix a possible hanging DisplayPort On some devices it can happen that DisplayPort TX lanes do not work properly if the power gate setup is omitted. If that happens, DisplayPort training will fail and therefore DisplayPort channel will not work. Both ports are affected. It seems that not every CPU shows this effect and those that are affected tend to fail more often in a cold environment. With this fix a board that originally shows this failure was running for over 1000 power cycles without issues. Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/13743 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Paul Menzel --- src/soc/intel/fsp_baytrail/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/fsp_baytrail/Makefile.inc') diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 79fc7eb79c..41672e6abf 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -3,6 +3,7 @@ # # Copyright (C) 2010 Google Inc. # Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2016 Siemens AG # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -54,6 +55,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c +ramstage-(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp -- cgit v1.2.3