From 0ecdf3e5361414bd345f414e922b57ffdd60e898 Mon Sep 17 00:00:00 2001
From: hcl-coreboot <Coreboot@hcl.com>
Date: Tue, 6 Aug 2019 15:40:23 +0530
Subject: fsp_baytrail/fsp_broadwell_de: Sort entries in Makefile.inc
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Change-Id: I12e6ec4aec7dcadcbb886c3fc4c3b9126a0a835c
Signed-off-by: Sourabh Kashyap <sourabhka@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/soc/intel/fsp_baytrail/Makefile.inc     | 48 ++++++++++++++++-------------
 src/soc/intel/fsp_baytrail/fsp/Makefile.inc |  2 +-
 2 files changed, 27 insertions(+), 23 deletions(-)

(limited to 'src/soc/intel/fsp_baytrail')

diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 3a58be9afd..fa719320ee 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -17,47 +17,51 @@
 
 ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
 
+subdirs-y += fsp
 subdirs-y += romstage
+subdirs-y += ../../../cpu/intel/microcode
+subdirs-y += ../../../cpu/intel/turbo
+subdirs-y += ../../../cpu/x86/cache
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
-subdirs-y += ../../../cpu/x86/cache
-subdirs-y += ../../../cpu/intel/microcode
-subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../lib/fsp
-subdirs-y += fsp
 
-ramstage-y += memmap.c
+romstage-y += gpio.c
+romstage-y += iosf.c
 romstage-y += memmap.c
-ramstage-y += tsc_freq.c
+romstage-y += pmutil.c
+romstage-y += spi.c
 romstage-y += tsc_freq.c
+
 postcar-y += tsc_freq.c
-smm-y += tsc_freq.c
-ramstage-y += spi.c
-romstage-y += spi.c
-smm-y += spi.c
+
+ramstage-y += acpi.c
 ramstage-y += chip.c
+ramstage-y += cpu.c
+ramstage-y += gfx.c
+ramstage-y += gpio.c
+ramstage-y += i2c.c
 ramstage-y += iosf.c
-romstage-y += iosf.c
+ramstage-y += lpe.c
+ramstage-y += lpss.c
+ramstage-y += memmap.c
 ramstage-y += northcluster.c
-ramstage-y += ramstage.c
-ramstage-y += gpio.c
-romstage-y += gpio.c
-romstage-y += pmutil.c
 ramstage-y += pmutil.c
+ramstage-y += ramstage.c
 ramstage-y += southcluster.c
-ramstage-y += cpu.c
-ramstage-y += acpi.c
-ramstage-y += lpe.c
-ramstage-y += lpss.c
+ramstage-y += spi.c
+ramstage-y += tsc_freq.c
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
+
 smm-y += pmutil.c
 smm-y += smihandler.c
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
+smm-y += spi.c
+smm-y += tsc_freq.c
 
+# Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
-ramstage-y += i2c.c
-ramstage-y += gfx.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
diff --git a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc
index 09c5bc506d..024dd70855 100644
--- a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc
@@ -13,5 +13,5 @@
 # GNU General Public License for more details.
 #
 
-ramstage-y += chipset_fsp_util.c
 romstage-y += chipset_fsp_util.c
+ramstage-y += chipset_fsp_util.c
-- 
cgit v1.2.3