From 97c0979befedb822e9d77bc0e11374e291332c49 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Thu, 6 Apr 2017 10:01:24 +0200 Subject: fsp_broadwell_de: Add SMM code Add basic SMM support for Broadwell-DE SoC. The code is mainly based on the SMM implementation of Broadwell with a few differences: - EMRR is now called PRMRR and the UNCORE part of it is not available - SMM_FEATURE_CONTROL is no longer a MSR but is now located in PCI space - currently only SERIRQ-SMI has a handler Change-Id: I461a14d411aedefdb0cb54ae43b91103a80a4f6a Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/19145 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/fsp_broadwell_de/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/fsp_broadwell_de/Makefile.inc') diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 657f70c936..028c45d6dc 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -5,6 +5,7 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../lib/fsp @@ -23,6 +24,11 @@ ramstage-y += reset.c ramstage-y += acpi.c ramstage-y += smbus_common.c ramstage-y += smbus.c +ramstage-y += smi.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp -- cgit v1.2.3