From d7cba288e4eb17e6e5c80b7ac4465357e0fbd31a Mon Sep 17 00:00:00 2001 From: York Yang Date: Wed, 9 Mar 2016 10:54:26 -0800 Subject: soc/intel: Add Broadwell-DE SoC support Initial files to support Broadwell-DE SoC. This is FSP 1.0 based project and is based on Broadwell-DE Gold release. Change has been verified on Intel Camelback Mountain CRB. Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57 Signed-off-by: York Yang Reviewed-on: https://review.coreboot.org/14014 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Martin Roth --- src/soc/intel/fsp_broadwell_de/Makefile.inc | 35 +++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 src/soc/intel/fsp_broadwell_de/Makefile.inc (limited to 'src/soc/intel/fsp_broadwell_de/Makefile.inc') diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc new file mode 100644 index 0000000000..a0d5203fc4 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -0,0 +1,35 @@ +ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) + +subdirs-y += romstage +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/cache +subdirs-y += ../../../lib/fsp +subdirs-y += fsp + +ramstage-y += spi.c +ramstage-y += cpu.c +ramstage-y += chip.c +ramstage-y += northcluster.c +ramstage-y += ramstage.c +romstage-y += memmap.c +ramstage-y += memmap.c +ramstage-y += southcluster.c +romstage-y += reset.c +ramstage-y += reset.c +ramstage-y += acpi.c + +ifeq ($(CONFIG_INTEGRATED_UART),y) +romstage-y += uart.c +ramstage-y += uart.c +smm-$(CONFIG_DEBUG_SMI) += uart.c +endif + +CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include +CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp +CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/ + +endif # ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) -- cgit v1.2.3