From 26d706bb333827c983abf7d734ce5af621d7adeb Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 20 Nov 2018 13:20:31 +0530 Subject: soc/intel/icelake: Create macros for FSP consumption 1. Modify PCIEXBAR to accomodate Type-C Root Port 2. LPSS device mode selection Change-Id: Ib7e4bc304f93e4b63ac2d7f194ca441dd96dd943 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/29697 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/include/soc/serialio.h | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) (limited to 'src/soc/intel/icelake/include') diff --git a/src/soc/intel/icelake/include/soc/serialio.h b/src/soc/intel/icelake/include/soc/serialio.h index 30a48a146f..cdf55157ff 100644 --- a/src/soc/intel/icelake/include/soc/serialio.h +++ b/src/soc/intel/icelake/include/soc/serialio.h @@ -16,27 +16,33 @@ #ifndef _SERIALIO_H_ #define _SERIALIO_H_ -typedef enum { +enum { PchSerialIoDisabled, PchSerialIoPci, - PchSerialIoAcpi, PchSerialIoHidden, -} PCH_SERIAL_IO_MODE; + PchSerialIoLegacyUart, + PchSerialIoSkipInit +}; -typedef enum { +enum { PchSerialIoIndexI2C0, PchSerialIoIndexI2C1, PchSerialIoIndexI2C2, PchSerialIoIndexI2C3, PchSerialIoIndexI2C4, - PchSerialIoIndexI2C5, - PchSerialIoIndexSPI0, - PchSerialIoIndexSPI1, - PchSerialIoIndexSPI2, + PchSerialIoIndexI2C5 +}; + +enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2 +}; + +enum { PchSerialIoIndexUART0, PchSerialIoIndexUART1, - PchSerialIoIndexUART2, - PchSerialIoIndexMAX -} PCH_SERIAL_IO_CONTROLLER; + PchSerialIoIndexUART2 +}; #endif -- cgit v1.2.3