From 34508cd9ac51021721f3e9abfe2a69c8a9835a4b Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Thu, 19 Apr 2018 18:03:46 +0530 Subject: soc/intel/icelake: Add PM timer emulation support in ICL CPU PM TIMER EMULATION logic will help UEFI payload to execute rather wait for time tick in absence of TCO and ACPI PM timer after FSP-S. BUG=N/A TEST=Able to build and boot with tianocore payload. Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff Signed-off-by: Aamir Bohra Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/31609 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/icelake/include/soc/cpu.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/icelake/include') diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index 1e8d9e86c4..b5722da742 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -35,6 +35,9 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 +/* Common Timer Copy (CTC) frequency - 38.4MHz. */ +#define CTC_FREQ 38400000 + #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ -- cgit v1.2.3